Attachment 'gbspec.txt'

Download

   1 ============================================================================
   2             Everything You Always Wanted To Know About GAMEBOY *
   3 ============================================================================
   4 
   5                         * but were afraid to ask
   6 
   7 
   8              Pan of -ATX- Document Updated by contributions from:
   9           Marat Fayzullin, Pascal Felber, Paul Robson, Martin Korth
  10 
  11                       Last update 7-Mar-08 by John Harrison
  12 
  13  Forward: The following was typed up for informational purposes regarding
  14           the inner workings on the hand-held game machine known as
  15           GameBoy, manufactured and designed by Nintendo Co., LTD.
  16           This info is presented to inform a user on how their Game Boy
  17           works and what makes it "tick". GameBoy is copyrighted by
  18           Nintendo Co., LTD. Any reference to copyrighted material is
  19           not presented for monetary gain, but for educational purposes
  20           and higher learning.
  21 
  22 Terms
  23 -----
  24 
  25  GB = Original GameBoy
  26  GBP = GameBoy Pocket/GameBoy Light
  27  GBC = GameBoy Colo(u)r
  28  SGB = Super GameBoy
  29 
  30 
  31 Game Boy Specs
  32 --------------
  33 
  34  CPU: 8-bit (Similar to the Z80 processor.)
  35  Main RAM: 8K Byte
  36  Video RAM: 8K Byte
  37  Screen Size 2.6"
  38  Resolution: 160x144 (20x18 tiles)
  39  Max # of sprites: 40
  40  Max # sprites/line: 10
  41  Max sprite size: 8x16
  42  Min sprite size: 8x8
  43  Clock Speed: 4.194304 MHz (4.295454 SGB, 4.194/8.388MHz GBC)
  44  Horiz Sync: 9198 KHz (9420 KHz for SGB)
  45  Vert Sync: 59.73 Hz (61.17 Hz for SGB)
  46  Sound: 4 channels with stereo sound
  47  Power: DC6V 0.7W (DC3V 0.7W for GB Pocket)
  48 
  49 
  50 Processor
  51 ---------
  52 
  53   The GameBoy uses a computer chip similar to an Intel 8080.
  54  It contains all of the instructions of an 8080 except there
  55  are no exchange instructions. In many ways the processor is
  56  more similar to the Zilog Z80 processor. Compared to the
  57  Z80, some instructions have been added and some have been
  58  taken away.
  59 
  60  The following are added instructions:
  61 
  62   ADD  SP,nn             ;nn = signed byte
  63   LD  (HLI),A            ;Write A to (HL) and increment HL
  64   LD  (HLD),A            ;Write A to (HL) and decrement HL
  65   LD  A,(HLI)            ;Write (HL) to A and increment HL
  66   LD  A,(HLD)            ;Write (HL) to A and decrement HL
  67   LD  A,($FF00+nn)
  68   LD  A,($FF00+C)
  69   LD  ($FF00+nn),A
  70   LD  ($FF00+C),A
  71   LD  (nnnn),SP
  72   LD  HL,SP+nn           ;nn = signed byte
  73   STOP                   ;Stop processor & screen until button press
  74   SWAP r                 ;Swap high & low nibbles of r
  75 
  76  The following instructions have been removed:
  77 
  78   Any command that uses the IX or IY registers.
  79   All IN/OUT instructions.
  80   All exchange instructions.
  81   All commands prefixed by ED (except remapped RETI).
  82   All conditional jumps/calls/rets on parity/overflow and sign flag.
  83 
  84  The following instructions have different opcodes:
  85 
  86   LD  A,[nnnn]
  87   LD  [nnnn],A
  88   RETI
  89 
  90 
  91 GB General Memory Map*
  92 ---------------------
  93 
  94   Interrupt Enable Register
  95  --------------------------- FFFF
  96   Internal RAM
  97  --------------------------- FF80
  98   Empty but unusable for I/O
  99  --------------------------- FF4C
 100   I/O ports
 101  --------------------------- FF00
 102   Empty but unusable for I/O
 103  --------------------------- FEA0
 104   Sprite Attrib Memory (OAM)
 105  --------------------------- FE00
 106   Echo of 8kB Internal RAM
 107  --------------------------- E000
 108   8kB Internal RAM
 109  --------------------------- C000
 110   8kB switchable RAM bank
 111  --------------------------- A000
 112   8kB Video RAM
 113  --------------------------- 8000
 114   32kB Cartridge
 115  --------------------------- 0000
 116 
 117 
 118  * NOTE: b = bit, B = byte
 119 
 120 
 121 Echo of 8kB Internal RAM
 122 ------------------------
 123 
 124  The addresses E000-FE00 appear to access the internal RAM
 125 the same as C000-DE00. (i.e. If you write a byte to address
 126 E000 it will appear at C000 and E000. Similarly, writing a
 127 byte to C000 will appear at C000 and E000.)
 128 
 129 
 130 User I/O
 131 --------
 132 
 133  There are no empty spaces in the memory map for
 134 implementing input ports except the switchable RAM bank
 135 area (not an option on the Super Smart Card since it's
 136 RAM bank is always enabled).
 137 
 138  An output only port may be implemented anywhere between
 139 A000-FDFF. If implemented in a RAM area care should be
 140 taken to use an area of RAM not used for anything else.
 141 (FE00 and above can't be used because the CPU doesn't
 142 generate an external /WR for these locations.)
 143 
 144  If you have a cart with an MBC1, a ROM 4Mbit or smaller,
 145 and a RAM 8Kbyte or smaller (or no RAM) then you can use
 146 pins 6 & 7 of the MBC1 for 2 digital output pins for
 147 whatever purpose you wish. To use them you must first
 148 put the MBC1 into 4MbitROM/32KbyteRAM mode by writing
 149 01 to 6000. The two least significant bits you write
 150 to 4000 will then be output to these pins.
 151 
 152 
 153 Reserved Memory Locations
 154 -------------------------
 155 
 156 0000       Restart $00 Address (RST $00 calls this address.)
 157 
 158 0008       Restart $08 Address (RST $08 calls this address.)
 159 
 160 0010       Restart $10 Address (RST $10 calls this address.)
 161 
 162 0018       Restart $18 Address (RST $18 calls this address.)
 163 
 164 0020       Restart $20 Address (RST $20 calls this address.)
 165 
 166 0028       Restart $28 Address (RST $28 calls this address.)
 167 
 168 0030       Restart $30 Address (RST $30 calls this address.)
 169 
 170 0038       Restart $38 Address (RST $38 calls this address.)
 171 
 172 0040       Vertical Blank Interrupt Start Address
 173 
 174 0048       LCDC Status Interrupt Start Address
 175 
 176 0050       Timer Overflow Interrupt Start Address
 177 
 178 0058       Serial Transfer Completion Interrupt Start Address
 179 
 180 0060       High-to-Low of P10-P13 Interrupt Start Address
 181 
 182 An internal information area is located at 0100-014F in
 183 each cartridge. It contains the following values:
 184 
 185 0100-0103  This is the begin code execution point in a
 186            cart. Usually there is a NOP and a JP
 187            instruction here but not always.
 188 
 189 0104-0133  Scrolling Nintendo graphic:
 190            CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D
 191            00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99
 192            BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E
 193            ( PROGRAM WON'T RUN IF CHANGED!!!)
 194 
 195 0134-0142  Title of the game in UPPER CASE ASCII. If it
 196            is less than 16 characters then the remaining
 197            bytes are filled with 00's.
 198 
 199 0143       $80 = Color GB, $00 or other = not Color GB
 200 
 201 0144       Ascii hex digit, high nibble of licensee code (new).
 202 0145       Ascii hex digit, low nibble of licensee code (new).
 203            (These are normally $00 if [$014B] <> $33.)
 204 
 205 0146       GB/SGB Indicator (00 = GameBoy, 03 = Super GameBoy functions)
 206            (Super GameBoy functions won't work if <> $03.)
 207 
 208 0147       Cartridge type:
 209            0 - ROM ONLY                12 - ROM+MBC3+RAM
 210            1 - ROM+MBC1                13 - ROM+MBC3+RAM+BATT
 211            2 - ROM+MBC1+RAM            19 - ROM+MBC5
 212            3 - ROM+MBC1+RAM+BATT       1A - ROM+MBC5+RAM
 213            5 - ROM+MBC2                1B - ROM+MBC5+RAM+BATT
 214            6 - ROM+MBC2+BATTERY        1C - ROM+MBC5+RUMBLE
 215            8 - ROM+RAM                 1D - ROM+MBC5+RUMBLE+SRAM
 216            9 - ROM+RAM+BATTERY         1E - ROM+MBC5+RUMBLE+SRAM+BATT
 217            B - ROM+MMM01               1F - Pocket Camera
 218            C - ROM+MMM01+SRAM          FD - Bandai TAMA5
 219            D - ROM+MMM01+SRAM+BATT     FE - Hudson HuC-3
 220            F - ROM+MBC3+TIMER+BATT     FF - Hudson HuC-1
 221           10 - ROM+MBC3+TIMER+RAM+BATT
 222           11 - ROM+MBC3
 223 
 224 0148       ROM size:
 225              0 - 256Kbit =  32KByte =   2 banks
 226              1 - 512Kbit =  64KByte =   4 banks
 227              2 -   1Mbit = 128KByte =   8 banks
 228              3 -   2Mbit = 256KByte =  16 banks
 229              4 -   4Mbit = 512KByte =  32 banks
 230              5 -   8Mbit =   1MByte =  64 banks
 231              6 -  16Mbit =   2MByte = 128 banks
 232            $52 -   9Mbit = 1.1MByte =  72 banks
 233            $53 -  10Mbit = 1.2MByte =  80 banks
 234            $54 -  12Mbit = 1.5MByte =  96 banks
 235 
 236 0149       RAM size:
 237            0 - None
 238            1 -  16kBit =  2kB = 1 bank
 239            2 -  64kBit =  8kB = 1 bank
 240            3 - 256kBit = 32kB = 4 banks
 241            4 -   1MBit =128kB =16 banks
 242 
 243 014A       Destination code:
 244            0 - Japanese
 245            1 - Non-Japanese
 246 
 247 014B       Licensee code (old):
 248            33 - Check 0144/0145 for Licensee code.
 249            79 - Accolade
 250            A4 - Konami
 251            (Super GameBoy function won't work if <> $33.)
 252 
 253 014C       Mask ROM Version number (Usually $00)
 254 
 255 014D       Complement check
 256            (PROGRAM WON'T RUN ON GB IF NOT CORRECT!!!)
 257            (It will run on Super GB, however, if incorrect.)
 258 
 259 014E-014F  Checksum (higher byte first) produced by
 260            adding all bytes of a cartridge except for two
 261            checksum bytes and taking two lower bytes of
 262            the result. (GameBoy ignores this value.)
 263 
 264 
 265 Cartridge Types
 266 ---------------
 267 
 268 The following define the byte at cart location 0147:
 269 
 270  ROM ONLY
 271   This is a 32kB (256kb) ROM and occupies 0000-7FFF.
 272 
 273  MBC1 (Memory Bank Controller 1)
 274    MBC1 has two different maximum memory modes:
 275   16Mbit ROM/8KByte RAM  or  4Mbit ROM/32KByte RAM.
 276 
 277    The MBC1 defaults to 16Mbit ROM/8KByte RAM mode
 278   on power up. Writing a value (XXXXXXXS - X = Don't
 279   care, S = Memory model select) into 6000-7FFF area
 280   will select the memory model to use. S = 0 selects
 281   16/8 mode. S = 1 selects 4/32 mode.
 282 
 283    Writing a value (XXXBBBBB - X = Don't cares, B =
 284   bank select bits) into 2000-3FFF area will select an
 285   appropriate ROM bank at 4000-7FFF. Values of 0 and 1
 286   do the same thing and point to ROM bank 1. Rom bank 0
 287   is not accessible from 4000-7FFF and can only be read
 288   from 0000-3FFF.
 289 
 290   If memory model is set to 4/32:
 291     Writing a value (XXXXXXBB - X = Don't care, B =
 292    bank select bits) into 4000-5FFF area will select an
 293    appropriate RAM bank at A000-C000. Before you can
 294    read or write to a RAM bank you have to enable it by
 295    writing a XXXX1010 into 0000-1FFF area*. To disable
 296    RAM bank operations write any value but XXXX1010
 297    into 0000-1FFF area. Disabling a RAM bank probably
 298    protects that bank from false writes during power
 299    down of the GameBoy. (NOTE: Nintendo suggests values
 300    $0A to enable and $00 to disable RAM bank!!)
 301 
 302   If memory model is set to 16/8 mode:
 303     Writing a value (XXXXXXBB - X = Don't care, B =
 304    bank select bits) into 4000-5FFF area will set the
 305    two most significant ROM address lines.
 306 
 307   * NOTE: The Super Smart Card doesn't require this
 308    operation because it's RAM bank is ALWAYS enabled.
 309    Include this operation anyway to allow your code
 310    to work with both.
 311 
 312  MBC2 (Memory Bank Controller 2):
 313    This memory controller works much like the MBC1
 314   controller with the following exceptions:
 315 
 316    MBC2 will work with ROM sizes up to 2Mbit.
 317 
 318    Writing a value (XXXXBBBB - X = Don't cares, B =
 319   bank select bits) into 2100-21FF area will select an
 320   appropriate ROM bank at 4000-7FFF.
 321 
 322    RAM switching is not provided. Unlike the MBC1 which
 323   uses external RAM, MBC2 has 512 x 4 bits of RAM which
 324   is in the controller itself. It still requires an
 325   external battery to save data during power-off though.
 326 
 327    The least significant bit of the upper address byte
 328   must be zero to enable/disable cart RAM. For example
 329   the following addresses can be used to enable/disable
 330   cart RAM:
 331   0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.
 332   The suggested address range to use for MBC2 ram
 333   enable/disable is 0000-00FF.
 334 
 335    The least significant bit of the upper address byte
 336   must be one to select a ROM bank. For example the
 337   following addresses can be used to select a ROM bank:
 338   2100-21FF, 2300-23FF, 2500-25FF, ..., 3F00-3FFF.
 339   The suggested address range to use for MBC2 rom
 340   bank selection is 2100-21FF.
 341 
 342  MBC3 (Memory Bank Controller 3):
 343    This controller is similar to MBC1 except it accesses
 344   all 16mbits of ROM without requiring any writes to the
 345   4000-5FFF area.
 346     Writing a value (XBBBBBBB - X = Don't care, B =
 347   bank select bits) into 2000-3FFF area will select an
 348   appropriate ROM bank at 4000-7FFF.
 349 
 350    Also, this MBC has a built-in battery-backed Real
 351   Time Clock (RTC) not found in any other MBC. Some
 352   MBC3 carts do not support it (WarioLand II non-color
 353   version) but some do (Harvest Moon/Japanese version.)
 354 
 355  MBC5 (Memory Bank Controller 5):
 356    This controller is the first MBC that is guaranteed
 357   to run in GameBoy Color double-speed mode but it
 358   appears the other MBC's run fine in GBC double-speed
 359   mode as well.
 360 
 361    It is similar to the MBC3 (but no RTC) but can
 362   access up to 64mbits of ROM and up to 1mbit of RAM.
 363   The lower 8 bits of the 9-bit rom bank select is
 364   written to the 2000-2FFF area while the upper bit
 365   is written to the least significant bit of the
 366   3000-3FFF area.
 367 
 368     Writing a value (XXXXBBBB - X = Don't care, B =
 369   bank select bits) into 4000-5FFF area will select an
 370   appropriate RAM bank at A000-BFFF if the cart
 371   contains RAM. Ram sizes are 64kbit,256kbit, & 1mbit.
 372 
 373    Also, this is the first MBC that allows rom bank 0
 374   to appear in the 4000-7FFF range by writing $000
 375   to the rom bank select.
 376 
 377  Rumble Carts:
 378    Rumble carts use an MBC5 memory bank controller.
 379   Rumble carts can only have up to 256kbits of RAM.
 380   The highest RAM address line that allows 1mbit of
 381   RAM on MBC5 non-rumble carts is used as the motor
 382   on/off for the rumble cart.
 383 
 384     Writing a value (XXXXMBBB - X = Don't care, M =
 385   motor, B = bank select bits) into 4000-5FFF area
 386   will select an appropriate RAM bank at A000-BFFF
 387   if the cart contains RAM. RAM sizes are 64kbit or
 388   256kbits. To turn the rumble motor on set M = 1,
 389   M = 0 turns it off.
 390 
 391  HuC1 (Memory Bank / Infrared Controller):
 392    This controller made by Hudson Soft appears to be
 393   very similar to an MBC1 with the main difference
 394   being that it supports infrared LED input / output.
 395   The Japanese cart "Fighting Phoenix" (internal cart
 396   name: SUPER B DAMAN) is known to contain this chip.
 397 
 398  Bung Carts:
 399    The flash carts sold by Bung (http://www.bung.com.hk)
 400   on power up appear like an MBC5 cart except that
 401   writing $00 to the bank select register selects rom
 402   bank 1 instead of rom bank 0. Writing values to
 403   3000-3FFF area does nothing.
 404 
 405    Writing values (XXXXXXXS - X = Don't care, S = Select)
 406   to 6000-7FFF area selects MBC1 16/8 mode if S=0
 407   except that writes to 3000-3FFF area still do nothing.
 408   If S=1 then MBC5 mode is selected. (S=1 by default
 409   on power up.)
 410 
 411    Cart locations A000 & A100 act as special
 412   write only hardware control registers if a
 413   value of $c0 is written to 0000-1FFF area.
 414   These hardware control registers are used
 415   for setting up cart hardware for different
 416   games when the Bung cart is used as a Multicart
 417   for holding several different games.
 418 
 419 
 420 Power Up Sequence
 421 -----------------
 422 
 423   When the GameBoy is powered up, a 256 byte program
 424  starting at memory location 0 is executed. This program
 425  is located in a ROM inside the GameBoy. The first thing
 426  the program does is read the cartridge locations from
 427  $104 to $133 and place this graphic of a Nintendo logo
 428  on the screen at the top. This image is then scrolled
 429  until it is in the middle of the screen. Two musical
 430  notes are then played on the internal speaker. Again,
 431  the cartridge locations $104 to $133 are read but this
 432  time they are compared with a table in the internal rom.
 433  If any byte fails to compare, then the GameBoy stops
 434  comparing bytes and simply halts all operations.
 435 
 436  GB & GB Pocket:
 437       Next, the GameBoy starts adding all of the bytes
 438       in the cartridge from $134 to $14d. A value of 25
 439       decimal is added to this total. If the least
 440       significant byte of the result is a not a zero,
 441       then the GameBoy will stop doing anything.
 442 
 443  Super GB:
 444       Even though the GB & GBP check the memory locations
 445       from $134 to $14d, the SGB doesn't.
 446 
 447   If the above checks pass then the internal ROM is
 448  disabled and cartridge program execution begins at
 449  location $100 with the following register values:
 450 
 451    AF=$01-GB/SGB, $FF-GBP, $11-GBC
 452    F =$B0
 453    B =$00-GB/SGB/GBP/GBC, $01-GBA
 454    C =$13
 455    DE=$00D8
 456    HL=$014D
 457    Stack Pointer=$FFFE
 458    [$FF05] = $00   ; TIMA
 459    [$FF06] = $00   ; TMA
 460    [$FF07] = $00   ; TAC
 461    [$FF10] = $80   ; NR10 a.k.a. rAUD1SWEEP
 462    [$FF11] = $BF   ; NR11 a.k.a. rAUD1LEN
 463    [$FF12] = $F3   ; NR12 a.k.a. rAUD1ENV
 464    [$FF14] = $BF   ; NR14 a.k.a. rAUD1HIGH
 465    [$FF16] = $3F   ; NR21 a.k.a. rAUD2LEN
 466    [$FF17] = $00   ; NR22 a.k.a. rAUD2ENV
 467    [$FF19] = $BF   ; NR24 a.k.a. rAUD2HIGH
 468    [$FF1A] = $7F   ; NR30 a.k.a. rAUD3ENA
 469    [$FF1B] = $FF   ; NR31 a.k.a. rAUD3LEN
 470    [$FF1C] = $9F   ; NR32 a.k.a. rAUD3LEVEL
 471    [$FF1E] = $BF   ; NR33 a.k.a. rAUD3LOW
 472    [$FF20] = $FF   ; NR41 a.k.a. rAUD4LEN
 473    [$FF21] = $00   ; NR42 a.k.a. rAUD4ENV
 474    [$FF22] = $00   ; NR43 a.k.a. rAUD4POLY
 475    [$FF23] = $BF   ; NR44 a.k.a. rAUD4GO
 476    [$FF24] = $77   ; NR50 a.k.a. rAUDVOL
 477    [$FF25] = $F3   ; NR51 a.k.a. rAUDTERM
 478    [$FF26] = $F1-GB, $F0-SGB ; NR52
 479    [$FF40] = $91   ; LCDC
 480    [$FF42] = $00   ; SCY
 481    [$FF43] = $00   ; SCX
 482    [$FF45] = $00   ; LYC
 483    [$FF47] = $FC   ; BGP
 484    [$FF48] = $FF   ; OBP0
 485    [$FF49] = $FF   ; OBP1
 486    [$FF4A] = $00   ; WY
 487    [$FF4B] = $00   ; WX
 488    [$FFFF] = $00   ; IE
 489 
 490  It is not a good idea to assume the above values
 491 will always exist. A later version GameBoy could
 492 contain different values than these at reset.
 493 Always set these registers on reset rather than
 494 assume they are as above.
 495 
 496  Please note that GameBoy internal RAM on power up
 497 contains random data. All of the GameBoy emulators
 498 tend to set all RAM to value $00 on entry.
 499 
 500  Cart RAM the first time it is accessed on a real
 501 GameBoy contains random data. It will only contain
 502 known data if the GameBoy code initializes it to
 503 some value.
 504 
 505 Stop Mode
 506 ---------
 507 
 508   The STOP command halts the GameBoy processor
 509  and screen until any button is pressed. The GB
 510  and GBP screen goes white with a single dark
 511  horizontal line. The GBC screen goes black.
 512 
 513 
 514 Low-Power Mode
 515 --------------
 516 
 517   It is recommended that the HALT instruction be used
 518  whenever possible to reduce power consumption & extend
 519  the life of the batteries. This command stops the
 520  system clock reducing the power consumption of both
 521  the CPU and ROM.
 522 
 523   The CPU will remain suspended until an interrupt
 524  occurs at which point the interrupt is serviced and
 525  then the instruction immediately following the HALT
 526  is executed. If interrupts are disabled (DI) then
 527  halt doesn't suspend operation but it does cause
 528  the program counter to stop counting for one
 529  instruction on the GB,GBP, and SGB as mentioned below.
 530 
 531   Depending on how much CPU time is required by a game,
 532  the HALT instruction can extend battery life anywhere
 533  from 5 to 50% or possibly more.
 534 
 535  WARNING: The instruction immediately following the
 536   HALT instruction is "skipped" when interrupts are
 537   disabled (DI) on the GB,GBP, and SGB. As a result,
 538   always put a NOP after the HALT instruction. This
 539   instruction skipping doesn't occur when interrupts
 540   are enabled (EI).
 541    This "skipping" does not seem to occur on the
 542   GameBoy Color even in regular GB mode. ($143=$00)
 543 
 544  EXAMPLES from Martin Korth who documented this problem:
 545   (assuming interrupts disabled for all examples)
 546 
 547 1) This code causes the 'a' register to be incremented TWICE.
 548       76          halt
 549       3C          inc  a
 550 
 551 2) The next example is a bit more difficult. The following code
 552       76          halt
 553       FA 34 12    ld   a,(1234)
 554 
 555    is effectively executed as
 556 
 557       76          halt
 558       FA FA 34    ld   a,(34FA)
 559       12          ld   (de),a
 560 
 561 3) Finally an interesting side effect
 562       76          halt
 563       76          halt
 564 
 565     This combination hangs the cpu.
 566    The first HALT causes the second HALT to be repeated, which
 567    therefore causes the following command (=itself) to be
 568    repeated - again and again.
 569    Placing a NOP between the two halts would cause the NOP to
 570    be repeated once, the second HALT wouldn't lock the cpu.
 571 
 572   Below is suggested code for GameBoy programs:
 573 
 574   ; **** Main Game Loop ****
 575   Main:
 576         halt                    ; stop system clock
 577                                 ; return from halt when interrupted
 578         nop                     ; (See WARNING above.)
 579 
 580         ld      a,(VblnkFlag)
 581         or      a               ; V-Blank interrupt ?
 582         jr      z,Main          ; No, some other interrupt
 583 
 584         xor     a
 585         ld      (VblnkFlag),a   ; Clear V-Blank flag
 586 
 587         call    Controls        ; button inputs
 588         call    Game            ; game operation
 589 
 590         jr      Main
 591 
 592   ; **** V-Blank Interrupt Routine ****
 593   Vblnk:
 594         push    af
 595         push    bc
 596         push    de
 597         push    hl
 598 
 599         call    SpriteDma       ; Do sprite updates
 600 
 601         ld      a,1
 602         ld      (VblnkFlag),a
 603 
 604         pop     hl
 605         pop     de
 606         pop     bc
 607         pop     af
 608         reti
 609 
 610 
 611 Video
 612 -----
 613 
 614   The main GameBoy screen buffer (background) consists
 615  of 256x256 pixels or 32x32 tiles (8x8 pixels each). Only
 616  160x144 pixels can be displayed on the screen. Registers
 617  SCROLLX and SCROLLY hold the coordinates of background to
 618  be displayed in the left upper corner of the screen.
 619  Background wraps around the screen (i.e. when part of it
 620  goes off the screen, it appears on the opposite side.)
 621 
 622   An area of VRAM known as Background Tile Map contains
 623  the numbers of tiles to be displayed. It is organized as
 624  32 rows of 32 bytes each. Each byte contains a number of
 625  a tile to be displayed. Tile patterns are taken from the
 626  Tile Data Table located either at $8000-8FFF or
 627  $8800-97FF. In the first case, patterns are numbered with
 628  unsigned numbers from 0 to 255 (i.e. pattern #0 lies at
 629  address $8000). In the second case, patterns have signed
 630  numbers from -128 to 127 (i.e. pattern #0 lies at address
 631  $9000). The Tile Data Table address for the background
 632  can be selected by setting the LCDC register.
 633 
 634   There are two different Background Tile Maps. One is
 635  located from $9800-9Bff. The other from $9C00-9FFF.
 636  Only one of these can be viewed at any one time. The
 637  currently displayed background can be selected by
 638  setting the LCDC register.
 639 
 640   Besides background, there is also a "window" overlaying
 641  the background. The window is not scrollable i.e. it is
 642  always displayed starting from its left upper corner. The
 643  location of a window on the screen can be adjusted via
 644  WNDPOSX and WNDPOSY registers. Screen coordinates of the
 645  top left corner of a window are WNDPOSX-7,WNDPOSY. The
 646  tile numbers for the window are stored in the Tile Data
 647  Table. None of the windows tiles are ever transparent.
 648  Both the Background and the window share the same Tile
 649  Data Table.
 650 
 651   Both background and window can be disabled or enabled
 652  separately via bits in the LCDC register.
 653 
 654   If the window is used and a scan line interrupt disables
 655  it (either by writing to LCDC or by setting WX > 166)
 656  and a scan line interrupt a little later on enables it
 657  then the window will resume appearing on the screen at the
 658  exact position of the window where it left off earlier.
 659  This way, even if there are only 16 lines of useful graphics
 660  in the window, you could display the first 8 lines at the
 661  top of the screen and the next 8 lines at the bottom if
 662  you wanted to do so.
 663 
 664   WX may be changed during a scan line interrupt (to either
 665  cause a graphic distortion effect or to disable the window
 666  (WX>166) ) but changes to WY are not dynamic and won't
 667  be noticed until the next screen redraw.
 668 
 669   The tile images are stored in the Tile Pattern Tables.
 670  Each 8x8 image occupies 16 bytes, where each 2 bytes
 671  represent a line:
 672 
 673   Tile:                                     Image:
 674 
 675   .33333..                     .33333.. -> 01111100 -> $7C
 676   22...22.                                 01111100 -> $7C
 677   11...11.                     22...22. -> 00000000 -> $00
 678   2222222. <-- digits                      11000110 -> $C6
 679   33...33.     represent       11...11. -> 11000110 -> $C6
 680   22...22.     color                       00000000 -> $00
 681   11...11.     numbers         2222222. -> 00000000 -> $00
 682   ........                                 11111110 -> $FE
 683                                33...33. -> 11000110 -> $C6
 684                                            11000110 -> $C6
 685                                22...22. -> 00000000 -> $00
 686                                            11000110 -> $C6
 687                                11...11. -> 11000110 -> $C6
 688                                            00000000 -> $00
 689                                ........ -> 00000000 -> $00
 690                                            00000000 -> $00
 691 
 692   As it was said before, there are two Tile Pattern Tables
 693  at $8000-8FFF and at $8800-97FF. The first one can be used
 694  for sprites, the background, and the window display. Its
 695  tiles are numbered from 0 to 255. The second table can be
 696  used for the background and the window display and its tiles
 697  are numbered from -128 to 127.
 698 
 699 
 700 Sprites
 701 ------
 702 
 703   GameBoy video controller can display up to 40 sprites
 704  either in 8x8 or in 8x16 pixels. Because of a limitation
 705  of hardware, only ten sprites can be displayed per scan
 706  line. Sprite patterns have the same format as tiles, but
 707  they are taken from the Sprite Pattern Table located at
 708  $8000-8FFF and have unsigned numbering. Sprite
 709  attributes reside in the Sprite Attribute Table (OAM
 710  - Object Attribute Memory) at $FE00-FE9F. OAM is divided
 711  into 40 4-byte blocks each of which corresponds to a sprite.
 712 
 713   In 8x16 sprite mode, the least significant bit of the
 714  sprite pattern number is ignored and treated as 0.
 715 
 716   When sprites with different x coordinate values overlap,
 717  the one with the smaller x coordinate (closer to the left)
 718  will have priority and appear above any others.
 719 
 720   When sprites with the same x coordinate values overlap,
 721  they have priority according to table ordering. (i.e.
 722  $FE00 - highest, $FE04 - next highest, etc.)
 723 
 724   Please note that Sprite X=0, Y=0 hides a sprite. To
 725  display a sprite use the following formulas:
 726 
 727  SpriteScreenPositionX(Upper left corner of sprite) = SpriteX - 8
 728  SpriteScreenPositionY(Upper left corner of sprite) = SpriteY - 16
 729 
 730   To display a sprite in the upper left corner of the
 731  screen set sprite X=8, Y=16.
 732 
 733   Only 10 sprites can be displayed on any one line.
 734  When this limit is exceeded, the lower priority sprites
 735  (priorities listed above) won't be displayed. To keep
 736  unused sprites from affecting onscreen sprites set their
 737  Y coordinate to Y=0 or Y=>144+16. Just setting the X
 738  coordinate to X=0 or X=>160+8 on a sprite will hide it
 739  but it will still affect other sprites sharing the same
 740  lines.
 741 
 742  Blocks have the following
 743  format:
 744 
 745   Byte0  Y position on the screen
 746   Byte1  X position on the screen
 747   Byte2  Pattern number 0-255 (Unlike some tile
 748          numbers, sprite pattern numbers are unsigned.
 749          LSB is ignored (treated as 0) in 8x16 mode.)
 750   Byte3  Flags:
 751 
 752          Bit7  Priority
 753                If this bit is set to 0, sprite is displayed
 754                on top of background & window. If this bit
 755                is set to 1, then sprite will be hidden behind
 756                colors 1, 2, and 3 of the background & window.
 757                (Sprite only prevails over color 0 of BG & win.)
 758          Bit6  Y flip
 759                Sprite pattern is flipped vertically if
 760                this bit is set to 1.
 761          Bit5  X flip
 762                Sprite pattern is flipped horizontally if
 763                this bit is set to 1.
 764          Bit4  Palette number
 765                Sprite colors are taken from OBJ1PAL if
 766                this bit is set to 1 and from OBJ0PAL
 767                otherwise.
 768 
 769 
 770 Sprite RAM Bug
 771 --------------
 772 
 773   There is a flaw in the GameBoy hardware that causes
 774  trash to be written to OAM RAM if the following commands
 775  are used while their 16-bit content is in the range
 776  of $FE00 to $FEFF:
 777 
 778   inc xx     (xx = bc,de, or hl)
 779   dec xx
 780 
 781   ldi a,(hl)
 782   ldd a,(hl)
 783 
 784   ldi (hl),a
 785   ldd (hl),a
 786 
 787   Only sprites 1 & 2 ($FE00 & $FE04) are not affected
 788  by these instructions.
 789 
 790 
 791 Sound
 792 -----
 793 
 794   There are two sound channels connected to the output
 795  terminals SO1 and SO2. There is also a input terminal Vin
 796  connected to the cartridge. It can be routed to either of
 797  both output terminals. GameBoy circuitry allows producing
 798  sound in four different ways:
 799 
 800    Quadrangular wave patterns with sweep and envelope functions.
 801    Quadrangular wave patterns with envelope functions.
 802    Voluntary wave patterns from wave RAM.
 803    White noise with an envelope function.
 804 
 805   These four sounds can be controlled independantly and
 806  then mixed separately for each of the output terminals.
 807 
 808   Sound registers may be set at all times while producing
 809  sound.
 810 
 811   When setting the initial value of the envelope and
 812  restarting the length counter, set the initial flag to 1
 813  and initialize the data.
 814 
 815   Under the following situations the Sound ON flag is
 816  reset and the sound output stops:
 817 
 818   1. When the sound output is stopped by the length counter.
 819   2. When overflow occurs at the addition mode while sweep
 820      is operating at sound 1.
 821 
 822   When the Sound OFF flag for sound 3 (bit 7 of NR30) is
 823  set at 0, the cancellation of the OFF mode must be done
 824  by setting the sound OFF flag to 1. By initializing
 825  sound 3, it starts it's function.
 826 
 827   When the All Sound OFF flag (bit 7 of NR52) is set to 0,
 828  the mode registers for sounds 1,2,3, and 4 are reset and
 829  the sound output stops. (NOTE: The setting of each sounds
 830  mode register must be done after the All Sound OFF mode
 831  is cancelled. During the All Sound OFF mode, each sound
 832  mode register cannot be set.)
 833 
 834   NOTE: DURING THE ALL SOUND OFF MODE, GB POWER CONSUMPTION
 835  DROPS BY 16% OR MORE! WHILE YOUR PROGRAMS AREN'T USING
 836  SOUND THEN SET THE ALL SOUND OFF FLAG TO 0. IT DEFAULTS
 837  TO 1 ON RESET.
 838 
 839   These tend to be the two most important equations in
 840  converting between Hertz and GB frequency registers:
 841  (Sounds will have a 2.4% higher frequency on Super GB.)
 842 
 843      gb = 2048 - (131072 / Hz)
 844 
 845      Hz  = 131072 / (2048 - gb)
 846 
 847 
 848 Timer
 849 -----
 850 
 851   Sometimes it's useful to have a timer that interrupts at
 852  regular intervals for routines that require periodic or
 853  percise updates. The timer in the GameBoy has a selectable
 854  frequency of 4096, 16384, 65536, or 262144 Hertz. This
 855  frequency increments the Timer Counter (TIMA). When it
 856  overflows, it generates an interrupt. It is then loaded
 857  with the contents of Timer Modulo (TMA). The following
 858  are examples:
 859 
 860  ;This interval timer interrupts 4096 times per second
 861 
 862      ld  a,-1
 863      ld  ($FF06),a     ;Set TMA to divide clock by 1
 864      ld  a,4
 865      ld  ($FF07),a     ;Set clock to 4096 Hertz
 866 
 867  ;This interval timer interrupts 65536 times per second
 868 
 869      ld  a,-4
 870      ld  ($FF06),a     ;Set TMA to divide clock by 4
 871      ld  a,5
 872      ld  ($FF07),a     ;Set clock to 262144 Hertz
 873 
 874 
 875 Serial I/O
 876 ----------
 877 
 878   The serial I/O port on the Gameboy is a very simple setup
 879  and is crude compared to standard RS-232 (IBM-PC) or RS-485
 880  (Macintosh) serial ports. There are no start or stop bits
 881  so the programmer must be more creative when using this port.
 882 
 883   During a transfer, a byte is shifted in at the same time
 884  that a byte is shifted out. The rate of the shift is deter-
 885  mined by whether the clock source is internal or external.
 886  If internal, the bits are shifted out at a rate of 8192Hz
 887  (122 microseconds) per bit. The most significant bit is
 888  shifted in and out first.
 889 
 890   When the internal clock is selected, it drives the clock
 891  pin on the game link port and it stays high when not used.
 892  During a transfer it will go low eight times to clock
 893  in/out each bit.
 894 
 895   A programmer initates a serial transfer by setting bit 7
 896  of $FF02. This bit may be read and is automatically set
 897  to 0 at the completion of transfer. After this bit is set,
 898  an interrupt will then occur eight bit clocks later if the
 899  serial interrupt is enabled.
 900   If internal clock is selected and serial interrupt is
 901  enabled, this interrupt occurs 122*8 microseconds later.
 902   If external clock is selected and serial interrupt is
 903  enabled, an interrupt will occur eight bit clocks later.
 904 
 905   Initiating a serial transfer with external clock will
 906  wait forever if no external clock is present. This allows
 907  a certain amount of synchronization with each serial port.
 908 
 909   The state of the last bit shifted out determines the
 910  state of the output line until another transfer takes
 911  place.
 912 
 913   If a serial transfer with internal clock is performed
 914  and no external GameBoy is present, a value of $FF will
 915  be received in the transfer.
 916 
 917   The following code causes $75 to be shifted out the
 918  serial port and a byte to be shifted into $FF01:
 919 
 920     ld   a,$75
 921     ld  ($FF01),a
 922     ld   a,$81
 923     ld  ($FF02),a
 924 
 925 
 926 Interrupt Procedure
 927 -------------------
 928 
 929   The IME (interrupt master enable) flag is reset by DI and
 930  prohibits all interrupts. It is set by EI and acknowledges
 931  the interrupt setting by the IE register.
 932 
 933  1. When an interrupt is generated, the IF flag will be set.
 934  2. If the IME flag is set & the corresponding IE flag is
 935     set, the following 3 steps are performed.
 936  3. Reset the IME flag and prevent all interrupts.
 937  4. The PC (program counter) is pushed onto the stack.
 938  5. Jump to the starting address of the interrupt.
 939 
 940   Resetting of the IF register, which was the cause of the
 941  interrupt, is done by hardware.
 942 
 943   During the interrupt, pushing of registers to be used
 944  should be performed by the interrupt routine.
 945 
 946   Once the interrupt service is in progress, all the
 947  interrupts will be prohibited. However, if the IME flag
 948  and the IE flag are controlled, a number of interrupt
 949  services can be made possible by nesting.
 950 
 951   Return from an interrupt routine can be performed by
 952  either RETI or RET instruction.
 953 
 954   The RETI instruction enables interrupts after doing a
 955  return operation.
 956 
 957   If a RET is used as the final instruction in an interrupt
 958  routine, interrupts will remain disabled unless a EI was
 959  used in the interrupt routine or is used at a later time.
 960 
 961   The interrupt will be acknowledged during opcode fetch
 962  period of each instruction.
 963 
 964 
 965 Interrupt Descriptions
 966 ----------------------
 967 
 968   The following interrupts only occur if they have been
 969  enabled in the Interrupt Enable register ($FFFF) and
 970  if the interrupts have actually been enabled using the
 971  EI instruction.
 972 
 973   V-Blank -
 974 
 975    The V-Blank interrupt occurs ~59.7 times a second
 976    on a regular GB and ~61.1 times a second on a Super
 977    GB (SGB). This interrupt occurs at the beginning of
 978    the V-Blank period. During this period video hardware
 979    is not using video ram so it may be freely accessed.
 980    This period lasts approximately 1.1 milliseconds.
 981 
 982   LCDC Status -
 983 
 984    There are various reasons for this interrupt to occur
 985    as described by the STAT register ($FF40). One very
 986    popular reason is to indicate to the user when the
 987    video hardware is about to redraw a given LCD line.
 988    This can be useful for dynamically controlling the SCX/
 989    SCY registers ($FF43/$FF42) to perform special video
 990    effects.
 991 
 992   Timer Overflow -
 993 
 994    This interrupt occurs when the TIMA register ($FF05)
 995    changes from $FF to $00.
 996 
 997   Serial Transfer Completion -
 998 
 999    This interrupt occurs when a serial transfer has
1000    completed on the game link port.
1001 
1002   High-to-Low of P10-P13 -
1003 
1004    This interrupt occurs on a transition of any of the
1005    keypad input lines from high to low. Due to the fact
1006    that keypad "bounce"* is virtually always present,
1007    software should expect this interrupt to occur one
1008    or more times for every button press and one or more
1009    times for every button release.
1010 
1011    * - Bounce tends to be a side effect of any button
1012       making or breaking a connection. During these
1013       periods, it is very common for a small amount of
1014       oscillation between high & low states to take place.
1015 
1016 I/O Registers
1017 -------------
1018 
1019 FF00
1020    Name     - P1
1021    Contents - Register for reading joy pad info
1022               and determining system type.    (R/W)
1023 
1024            Bit 7 - Not used
1025            Bit 6 - Not used
1026            Bit 5 - P15 out port
1027            Bit 4 - P14 out port
1028            Bit 3 - P13 in port
1029            Bit 2 - P12 in port
1030            Bit 1 - P11 in port
1031            Bit 0 - P10 in port
1032 
1033          This is the matrix layout for register $FF00:
1034 
1035 
1036                  P14        P15
1037                   |          |
1038         P10-------O-Right----O-A
1039                   |          |
1040         P11-------O-Left-----O-B
1041                   |          |
1042         P12-------O-Up-------O-Select
1043                   |          |
1044         P13-------O-Down-----O-Start
1045                   |          |
1046 
1047        Example code:
1048 
1049           Game: Ms. Pacman
1050           Address: $3b1
1051 
1052         LD A,$20       <- bit 5 = $20
1053         LD ($FF00),A   <- select P14 by setting it low
1054         LD A,($FF00)
1055         LD A,($FF00)   <- wait a few cycles
1056         CPL            <- complement A
1057         AND $0F        <- get only first 4 bits
1058         SWAP A         <- swap it
1059         LD B,A         <- store A in B
1060         LD A,$10
1061         LD ($FF00),A   <- select P15 by setting it low
1062         LD A,($FF00)
1063         LD A,($FF00)
1064         LD A,($FF00)
1065         LD A,($FF00)
1066         LD A,($FF00)
1067         LD A,($FF00)   <- Wait a few MORE cycles
1068         CPL            <- complement (invert)
1069         AND $0F        <- get first 4 bits
1070         OR B           <- put A and B together
1071 
1072         LD B,A         <- store A in D
1073         LD A,($FF8B)   <- read old joy data from ram
1074         XOR B          <- toggle w/current button bit
1075         AND B          <- get current button bit back
1076         LD ($FF8C),A   <- save in new Joydata storage
1077         LD A,B         <- put original value in A
1078         LD ($FF8B),A   <- store it as old joy data
1079 
1080 
1081         LD A,$30       <- deselect P14 and P15
1082         LD ($FF00),A   <- RESET Joypad
1083         RET            <- Return from Subroutine
1084 
1085           The button values using the above method are such:
1086           $80 - Start             $8 - Down
1087           $40 - Select            $4 - Up
1088           $20 - B                 $2 - Left
1089           $10 - A                 $1 - Right
1090 
1091           Let's say we held down A, Start, and Up.
1092           The value returned in accumulator A would be $94
1093 
1094 
1095 FF01
1096    Name     - SB
1097    Contents - Serial transfer data (R/W)
1098 
1099               8 Bits of data to be read/written
1100 
1101 FF02
1102    Name     - SC
1103    Contents - SIO control  (R/W)
1104 
1105               Bit 7 - Transfer Start Flag
1106                       0: Non transfer
1107                       1: Start transfer
1108 
1109               Bit 0 - Shift Clock
1110                       0: External Clock (500KHz Max.)
1111                       1: Internal Clock (8192Hz)
1112 
1113                Transfer is initiated by setting the
1114               Transfer Start Flag. This bit may be read
1115               and is automatically set to 0 at the end of
1116               Transfer.
1117 
1118                Transmitting and receiving serial data is
1119               done simultaneously. The received data is
1120               automatically stored in SB.
1121 
1122 FF04
1123    Name     - DIV
1124    Contents - Divider Register (R/W)
1125 
1126               This register is incremented 16384 (~16779
1127               on SGB) times a second. Writing any value
1128               sets it to $00.
1129 FF05
1130    Name     - TIMA
1131    Contents - Timer counter (R/W)
1132 
1133               This timer is incremented by a clock frequency
1134               specified by the TAC register ($FF07). The timer
1135               generates an interrupt when it overflows.
1136 
1137 FF06
1138    Name     - TMA
1139    Contents - Timer Modulo (R/W)
1140 
1141               When the TIMA overflows, this data will be loaded.
1142 
1143 FF07
1144    Name     - TAC
1145    Contents - Timer Control (R/W)
1146 
1147               Bit 2 - Timer Stop
1148                       0: Stop Timer
1149                       1: Start Timer
1150 
1151               Bits 1+0 - Input Clock Select
1152                          00: 4.096 KHz    (~4.194 KHz SGB)
1153                          01: 262.144 KHz  (~268.4 KHz SGB)
1154                          10: 65.536 KHz   (~67.11 KHz SGB)
1155                          11: 16.384 KHz   (~16.78 KHz SGB)
1156 
1157 FF0F
1158    Name     - IF
1159    Contents - Interrupt Flag (R/W)
1160 
1161               Bit 4: Transition from High to Low of Pin number P10-P13
1162               Bit 3: Serial I/O transfer complete
1163               Bit 2: Timer Overflow
1164               Bit 1: LCDC (see STAT)
1165               Bit 0: V-Blank
1166 
1167    The priority and jump address for the above 5 interrupts are:
1168 
1169     Interrupt        Priority        Start Address
1170 
1171     V-Blank             1              $0040
1172     LCDC Status         2              $0048 - Modes 0, 1, 2
1173                                                LYC=LY coincide (selectable)
1174     Timer Overflow      3              $0050
1175     Serial Transfer     4              $0058 - when transfer is complete
1176     Hi-Lo of P10-P13    5              $0060
1177 
1178     * When more than 1 interrupts occur at the same time
1179       only the interrupt with the highest priority can be
1180       acknowledged. When an interrupt is used a '0' should
1181       be stored in the IF register before the IE register
1182       is set.
1183 
1184 
1185 FF10
1186    Name     - NR 10 --- AUD1SWEEP
1187    Contents - Sound Mode 1 register, Sweep register (R/W)
1188 
1189               Bit 6-4 - Sweep Time
1190               Bit 3   - Sweep Increase/Decrease
1191                          0: Addition    (frequency increases)
1192                          1: Subtraction (frequency decreases)
1193               Bit 2-0 - Number of sweep shift (n: 0-7)
1194 
1195               Sweep Time: 000: sweep off - no freq change
1196                           001: 7.8 ms  (1/128Hz)
1197                           010: 15.6 ms (2/128Hz)
1198                           011: 23.4 ms (3/128Hz)
1199                           100: 31.3 ms (4/128Hz)
1200                           101: 39.1 ms (5/128Hz)
1201                           110: 46.9 ms (6/128Hz)
1202                           111: 54.7 ms (7/128Hz)
1203 
1204               The change of frequency (NR13,NR14) at each shift
1205               is calculated by the following formula where
1206               X(0) is initial freq & X(t-1) is last freq:
1207 
1208                X(t) = X(t-1) +/- X(t-1)/2^n
1209 
1210 FF11
1211    Name     - NR 11 --- AUD1LEN
1212    Contents - Sound Mode 1 register, Sound length/Wave pattern duty (R/W)
1213 
1214               Only Bits 7-6 can be read.
1215 
1216               Bit 7-6 - Wave Pattern Duty
1217               Bit 5-0 - Sound length data (t1: 0-63)
1218 
1219               Wave Duty: 00: 12.5% ( _--------_--------_-------- )
1220                          01: 25%   ( __-------__-------__------- )
1221                          10: 50%   ( ____-----____-----____----- ) (default)
1222                          11: 75%   ( ______---______---______--- )
1223 
1224               Sound Length = (64-t1)*(1/256) seconds
1225 FF12
1226    Name     - NR 12 --- AUD1ENV
1227    Contents - Sound Mode 1 register, Envelope (R/W)
1228 
1229               Bit 7-4 - Initial volume of envelope
1230               Bit 3 -   Envelope UP/DOWN
1231                          0: Attenuate
1232                          1: Amplify
1233               Bit 2-0 - Number of envelope sweep (n: 0-7)
1234                         (If zero, stop envelope operation.)
1235 
1236               Initial volume of envelope is from 0 to $F.
1237               Zero being no sound.
1238 
1239               Length of 1 step = n*(1/64) seconds
1240 
1241 FF13
1242    Name     - NR 13 --- AUD1LOW
1243    Contents - Sound Mode 1 register, Frequency lo (W)
1244 
1245               Lower 8 bits of 11 bit frequency (x).
1246               Next 3 bit are in NR 14 ($FF14)
1247 
1248 FF14
1249    Name     - NR 14 --- AUD1HIGH
1250    Contents - Sound Mode 1 register, Frequency hi (R/W)
1251 
1252               Only Bit 6 can be read.
1253 
1254               Bit 7 - Initial (when set, sound restarts)
1255               Bit 6 - Counter/consecutive selection
1256               Bit 2-0 - Frequency's higher 3 bits (x)
1257 
1258               Frequency = 4194304/(32*(2048-x)) Hz
1259                         = 131072/(2048-x) Hz
1260 
1261               Counter/consecutive Selection
1262                0 = Regardless of the length data in NR11
1263                    sound can be produced consecutively.
1264                1 = Sound is generated during the time period
1265                    set by the length data in NR11. After this
1266                    period the sound 1 ON flag (bit 0 of NR52)
1267                    is reset.
1268 
1269 FF16
1270    Name     - NR 21 --- AUD2LEN
1271    Contents - Sound Mode 2 register, Sound Length; Wave Pattern Duty (R/W)
1272 
1273               Only bits 7-6 can be read.
1274 
1275               Bit 7-6 - Wave pattern duty
1276               Bit 5-0 - Sound length data (t1: 0-63)
1277 
1278               Wave Duty: 00: 12.5% ( _--------_--------_-------- )
1279                          01: 25%   ( __-------__-------__------- )
1280                          10: 50%   ( ____-----____-----____----- ) (default)
1281                          11: 75%   ( ______---______---______--- )
1282 
1283               Sound Length = (64-t1)*(1/256) seconds
1284 
1285 FF17
1286    Name     - NR 22 --- AUD2ENV
1287    Contents - Sound Mode 2 register, envelope (R/W)
1288 
1289               Bit 7-4 - Initial volume of envelope
1290               Bit 3 -   Envelope UP/DOWN
1291                          0: Attenuate
1292                          1: Amplify
1293               Bit 2-0 - Number of envelope sweep (n: 0-7)
1294                         (If zero, stop envelope operation.)
1295 
1296               Initial volume of envelope is from 0 to $F.
1297               Zero being no sound.
1298 
1299               Length of 1 step = n*(1/64) seconds
1300 
1301 FF18
1302    Name     - NR 23 --- AUD2LOW
1303    Contents - Sound Mode 2 register, frequency lo data (W)
1304 
1305               Frequency's lower 8 bits of 11 bit data (x).
1306               Next 3 bits are in NR 14 ($FF19).
1307 
1308 FF19
1309    Name     - NR 24 --- AUD2HIGH
1310    Contents - Sound Mode 2 register, frequency hi data (R/W)
1311 
1312               Only bit 6 can be read.
1313 
1314               Bit 7 - Initial (when set, sound restarts)
1315               Bit 6 - Counter/consecutive selection
1316               Bit 2-0 - Frequency's higher 3 bits (x)
1317 
1318               Frequency = 4194304/(32*(2048-x)) Hz
1319                         = 131072/(2048-x) Hz
1320 
1321               Counter/consecutive Selection
1322                0 = Regardless of the length data in NR21
1323                    sound can be produced consecutively.
1324                1 = Sound is generated during the time period
1325                    set by the length data in NR21. After this
1326                    period the sound 2 ON flag (bit 1 of NR52)
1327                    is reset.
1328 
1329 FF1A
1330    Name     - NR 30 --- AUD3ENA
1331    Contents - Sound Mode 3 register, Sound on/off (R/W)
1332 
1333               Only bit 7 can be read
1334 
1335               Bit 7 - Sound OFF
1336                       0: Sound 3 output stop
1337                       1: Sound 3 output OK
1338 
1339 FF1B
1340    Name     - NR 31 --- AUD3LEN
1341    Contents - Sound Mode 3 register, sound length (R/W)
1342 
1343               Bit 7-0 - Sound length (t1: 0 - 255)
1344 
1345               Sound Length = (256-t1)*(1/2) seconds
1346 
1347 FF1C
1348    Name     - NR 32 --- AUD3LEVEL
1349    Contents - Sound Mode 3 register, Select output level (R/W)
1350 
1351               Only bits 6-5 can be read
1352 
1353               Bit 6-5 - Select output level
1354                         00: Mute
1355                         01: Produce Wave Pattern RAM Data as it is
1356                             (4 bit length)
1357                         10: Produce Wave Pattern RAM data shifted once
1358                             to the RIGHT (1/2)  (4 bit length)
1359                         11: Produce Wave Pattern RAM data shifted twice
1360                             to the RIGHT (1/4)  (4 bit length)
1361 
1362        * - Wave Pattern RAM is located from $FF30-$FF3f.
1363 
1364 FF1D
1365    Name     - NR 33 --- AUD3LOW
1366    Contents - Sound Mode 3 register, frequency's lower data (W)
1367 
1368               Lower 8 bits of an 11 bit frequency (x).
1369 
1370 FF1E
1371    Name     - NR 34 --- AUD3HIGH
1372    Contents - Sound Mode 3 register, frequency's higher data (R/W)
1373 
1374               Only bit 6 can be read.
1375 
1376               Bit 7 - Initial (when set, sound restarts)
1377               Bit 6 - Counter/consecutive flag
1378               Bit 2-0 - Frequency's higher 3 bits (x).
1379 
1380               Frequency = 4194304/(64*(2048-x)) Hz
1381                         = 65536/(2048-x) Hz
1382 
1383               Counter/consecutive Selection
1384                0 = Regardless of the length data in NR31
1385                    sound can be produced consecutively.
1386                1 = Sound is generated during the time period
1387                    set by the length data in NR31. After this
1388                    period the sound 3 ON flag (bit 2 of NR52)
1389                    is reset.
1390 
1391 FF20
1392    Name     - NR 41 --- AUD4LEN
1393    Contents - Sound Mode 4 register, sound length (R/W)
1394 
1395               Bit 5-0 - Sound length data (t1: 0-63)
1396 
1397               Sound Length = (64-t1)*(1/256) seconds
1398 
1399 FF21
1400    Name     - NR 42 --- AUD4ENV
1401    Contents - Sound Mode 4 register, envelope (R/W)
1402 
1403               Bit 7-4 - Initial volume of envelope
1404               Bit 3 -   Envelope UP/DOWN
1405                          0: Attenuate
1406                          1: Amplify
1407               Bit 2-0 - Number of envelope sweep (n: 0-7)
1408                         (If zero, stop envelope operation.)
1409 
1410               Initial volume of envelope is from 0 to $F.
1411               Zero being no sound.
1412 
1413               Length of 1 step = n*(1/64) seconds
1414 
1415 FF22
1416    Name     - NR 43 --- AUD4POLY
1417    Contents - Sound Mode 4 register, polynomial counter (R/W)
1418 
1419               Bit 7-4 - Selection of the shift clock frequency of the
1420                         polynomial counter
1421               Bit 3   - Selection of the polynomial counter's step
1422               Bit 2-0 - Selection of the dividing ratio of frequencies
1423 
1424               Selection of the dividing ratio of frequencies:
1425               000: f * 1/2^3 * 2
1426               001: f * 1/2^3 * 1
1427               010: f * 1/2^3 * 1/2
1428               011: f * 1/2^3 * 1/3
1429               100: f * 1/2^3 * 1/4
1430               101: f * 1/2^3 * 1/5
1431               110: f * 1/2^3 * 1/6
1432               111: f * 1/2^3 * 1/7           f = 4.194304 Mhz
1433 
1434               Selection of the polynomial counter step:
1435               0: 15 steps
1436               1: 7 steps
1437 
1438               Selection of the shift clock frequency of the polynomial
1439               counter:
1440 
1441               0000: dividing ratio of frequencies * 1/2
1442               0001: dividing ratio of frequencies * 1/2^2
1443               0010: dividing ratio of frequencies * 1/2^3
1444               0011: dividing ratio of frequencies * 1/2^4
1445                     :                          :
1446                     :                          :
1447                     :                          :
1448               0101: dividing ratio of frequencies * 1/2^14
1449               1110: prohibited code
1450               1111: prohibited code
1451 
1452 FF23
1453    Name     - NR 44 --- AUD4GO
1454    Contents - Sound Mode 4 register, counter/consecutive; inital (R/W)
1455 
1456               Only bit 6 can be read.
1457 
1458               Bit 7 - Initial (when set, sound restarts)
1459               Bit 6 - Counter/consecutive selection
1460 
1461               Counter/consecutive Selection
1462                0 = Regardless of the length data in NR41
1463                    sound can be produced consecutively.
1464                1 = Sound is generated during the time period
1465                    set by the length data in NR41. After this
1466                    period the sound 4 ON flag (bit 3 of NR52)
1467                    is reset.
1468 
1469 FF24
1470    Name     - NR 50 --- AUDVOL
1471    Contents - Channel control / ON-OFF / Volume (R/W)
1472 
1473               Bit 7 - Vin->SO2 ON/OFF
1474               Bit 6-4 - SO2 output level (volume) (# 0-7)
1475               Bit 3 - Vin->SO1 ON/OFF
1476               Bit 2-0 - SO1 output level (volume) (# 0-7)
1477 
1478               Vin->SO1 (Vin->SO2)
1479 
1480               By synthesizing the sound from sound 1
1481               through 4, the voice input from Vin
1482               terminal is put out.
1483               0: no output
1484               1: output OK
1485 
1486 FF25
1487     Name     - NR 51 --- AUDTERM
1488     Contents - Selection of Sound output terminal (R/W)
1489 
1490                Bit 7 - Output sound 4 to SO2 terminal
1491                Bit 6 - Output sound 3 to SO2 terminal
1492                Bit 5 - Output sound 2 to SO2 terminal
1493                Bit 4 - Output sound 1 to SO2 terminal
1494                Bit 3 - Output sound 4 to SO1 terminal
1495                Bit 2 - Output sound 3 to SO1 terminal
1496                Bit 1 - Output sound 2 to SO1 terminal
1497                Bit 0 - Output sound 1 to SO1 terminal
1498 
1499 FF26
1500     Name     - NR 52  --- AUDENA (Value at reset: $F1-GB, $F0-SGB)
1501     Contents - Sound on/off (R/W)
1502 
1503                Bit 7 - All sound on/off
1504                        0: stop all sound circuits
1505                        1: operate all sound circuits
1506                Bit 3 - Sound 4 ON flag
1507                Bit 2 - Sound 3 ON flag
1508                Bit 1 - Sound 2 ON flag
1509                Bit 0 - Sound 1 ON flag
1510 
1511                 Bits 0 - 3 of this register are meant to
1512                be status bits to be read. Writing to these
1513                bits does NOT enable/disable sound.
1514 
1515                 If your GB programs don't use sound then
1516                write $00 to this register to save 16% or
1517                more on GB power consumption.
1518 FF30 - FF3F
1519    Name     - Wave Pattern RAM
1520    Contents - Waveform storage for arbitrary sound data
1521 
1522               This storage area holds 32 4-bit samples
1523               that are played back upper 4 bits first.
1524 
1525 FF40
1526    Name     - LCDC  (value $91 at reset)
1527    Contents - LCD Control (R/W)
1528 
1529               Bit 7 - LCD Control Operation *
1530                       0: Stop completely (no picture on screen)
1531                       1: operation
1532 
1533               Bit 6 - Window Tile Map Display Select
1534                       0: $9800-$9BFF
1535                       1: $9C00-$9FFF
1536 
1537               Bit 5 - Window Display
1538                       0: off
1539                       1: on
1540 
1541               Bit 4 - BG & Window Tile Data Select
1542                       0: $8800-$97FF
1543                       1: $8000-$8FFF <- Same area as OBJ
1544 
1545               Bit 3 - BG Tile Map Display Select
1546                       0: $9800-$9BFF
1547                       1: $9C00-$9FFF
1548 
1549               Bit 2 - OBJ (Sprite) Size
1550                       0: 8*8
1551                       1: 8*16 (width*height)
1552 
1553               Bit 1 - OBJ (Sprite) Display
1554                       0: off
1555                       1: on
1556 
1557               Bit 0 - BG & Window Display
1558                       0: off
1559                       1: on
1560 
1561        * - Stopping LCD operation (bit 7 from 1 to 0)
1562            must be performed during V-blank to work
1563            properly. V-blank can be confirmed when the
1564            value of LY is greater than or equal to 144.
1565 
1566 FF41
1567    Name     - STAT
1568    Contents - LCDC Status   (R/W)
1569 
1570               Bits 6-3 - Interrupt Selection By LCDC Status
1571 
1572               Bit 6 - LYC=LY Coincidence (Selectable)
1573               Bit 5 - Mode 10
1574               Bit 4 - Mode 01
1575               Bit 3 - Mode 00
1576                       0: Non Selection
1577                       1: Selection
1578 
1579               Bit 2 - Coincidence Flag
1580                       0: LYC not equal to LCDC LY
1581                       1: LYC = LCDC LY
1582 
1583               Bit 1-0 - Mode Flag
1584                         00: During H-Blank
1585                         01: During V-Blank
1586                         10: During Searching OAM-RAM
1587                         11: During Transfering Data to LCD Driver
1588 
1589      STAT shows the current status of the LCD controller.
1590      Mode 00: When the flag is 00 it is the H-Blank period
1591               and the CPU can access the display RAM
1592               ($8000-$9FFF).
1593 
1594      Mode 01: When the flag is 01 it is the V-Blank period
1595               and the CPU can access the display RAM
1596               ($8000-$9FFF).
1597 
1598      Mode 10: When the flag is 10 then the OAM is being
1599               used ($FE00-$FE9F). The CPU cannot access
1600               the OAM during this period
1601 
1602      Mode 11: When the flag is 11 both the OAM and display
1603               RAM are being used. The CPU cannot access
1604               either during this period.
1605 
1606 
1607      The following are typical when the display is enabled:
1608 
1609 Mode 0  000___000___000___000___000___000___000________________
1610 Mode 1  _______________________________________11111111111111__
1611 Mode 2  ___2_____2_____2_____2_____2_____2___________________2_
1612 Mode 3  ____33____33____33____33____33____33__________________3
1613 
1614 
1615        The Mode Flag goes through the values 0, 2,
1616       and 3 at a cycle of about 109uS. 0 is present
1617       about 48.6uS, 2 about 19uS, and 3 about 41uS. This
1618       is interrupted every 16.6ms by the VBlank (1).
1619       The mode flag stays set at 1 for about 1.08 ms.
1620       (Mode 0 is present between 201-207 clks, 2 about
1621        77-83 clks, and 3 about 169-175 clks. A complete
1622        cycle through these states takes 456 clks.
1623        VBlank lasts 4560 clks. A complete screen refresh
1624        occurs every 70224 clks.)
1625 
1626 FF42
1627    Name     - SCY
1628    Contents - Scroll Y   (R/W)
1629 
1630               8 Bit value $00-$FF to scroll BG Y screen
1631               position.
1632 
1633 FF43
1634    Name     - SCX
1635    Contents - Scroll X   (R/W)
1636 
1637               8 Bit value $00-$FF to scroll BG X screen
1638               position.
1639 
1640 FF44
1641    Name     - LY
1642    Contents - LCDC Y-Coordinate (R)
1643 
1644             The LY indicates the vertical line to which
1645             the present data is transferred to the LCD
1646             Driver. The LY can take on any value between
1647             0 through 153. The values between 144 and 153
1648             indicate the V-Blank period. Writing will
1649             reset the counter.
1650 
1651 FF45
1652    Name     - LYC
1653    Contents - LY Compare  (R/W)
1654 
1655             The LYC compares itself with the LY. If the
1656             values are the same it causes the STAT to set
1657             the coincident flag.
1658 
1659 FF46
1660    Name     - DMA
1661    Contents - DMA Transfer and Start Address (W)
1662 
1663    The DMA Transfer (40*28 bit) from internal ROM or RAM
1664    ($0000-$F19F) to the OAM (address $FE00-$FE9F) can be
1665    performed. It takes 160 microseconds for the transfer.
1666 
1667    40*28 bit = #140  or #$8C.  As you can see, it only
1668    transfers $8C bytes of data. OAM data is $A0 bytes
1669    long, from $0-$9F.
1670 
1671    But if you examine the OAM data you see that 4 bits are
1672    not in use.
1673 
1674    40*32 bit = #$A0, but since 4 bits for each OAM is not
1675    used it's 40*28 bit.
1676 
1677    It transfers all the OAM data to OAM RAM.
1678 
1679    The DMA transfer start address can be designated every
1680    $100 from address $0000-$F100. That means $0000, $0100,
1681    $0200, $0300....
1682 
1683     As can be seen by looking at register $FF41 Sprite RAM
1684    ($FE00 - $FE9F) is not always available. A simple routine
1685    that many games use to write data to Sprite memory is shown
1686    below. Since it copies data to the sprite RAM at the appro-
1687    priate times it removes that responsibility from the main
1688    program.
1689     All of the memory space, except high ram ($FF80-$FFFE),
1690    is not accessible during DMA. Because of this, the routine
1691    below must be copied & executed in high ram. It is usually
1692    called from a V-blank Interrupt.
1693 
1694    Example program:
1695 
1696       org $40
1697       jp VBlank
1698 
1699       org $ff80
1700 VBlank:
1701       push af        <- Save A reg & flags
1702       ld a,BASE_ADRS <- transfer data from BASE_ADRS
1703       ld ($ff46),a   <- put A into DMA registers
1704       ld a,28h       <- loop length
1705 Wait:                <- We need to wait 160 microseconds.
1706       dec a          <-  4 cycles - decrease A by 1
1707       jr nz,Wait     <- 12 cycles - branch if Not Zero to Wait
1708       pop af         <- Restore A reg & flags
1709       reti           <- Return from interrupt
1710 
1711 
1712 FF47
1713    Name     - BGP
1714    Contents - BG & Window Palette Data  (R/W)
1715 
1716               Bit 7-6 - Data for Dot Data 11 (Normally darkest color)
1717               Bit 5-4 - Data for Dot Data 10
1718               Bit 3-2 - Data for Dot Data 01
1719               Bit 1-0 - Data for Dot Data 00 (Normally lightest color)
1720 
1721               This selects the shade of grays to use for
1722               the background (BG) & window pixels. Since
1723               each pixel uses 2 bits, the corresponding
1724               shade will be selected from here.
1725 
1726 FF48
1727    Name     - OBP0
1728    Contents - Object Palette 0 Data (R/W)
1729 
1730               This selects the colors for sprite palette 0.
1731               It works exactly as BGP ($FF47) except each
1732               each value of 0 is transparent.
1733 
1734 FF49
1735    Name     - OBP1
1736    Contents - Object Palette 1 Data (R/W)
1737 
1738               This Selects the colors for sprite palette 1.
1739               It works exactly as OBP0 ($FF48).
1740               See BGP for details.
1741 
1742 FF4A
1743    Name     - WY
1744    Contents - Window Y Position  (R/W)
1745 
1746               0 <= WY <= 143
1747 
1748               WY must be greater than or equal to 0 and
1749               must be less than or equal to 143 for
1750               window to be visible.
1751 
1752 FF4B
1753    Name     - WX
1754    Contents - Window X Position  (R/W)
1755 
1756               0 <= WX <= 166
1757 
1758               WX must be greater than or equal to 0 and
1759               must be less than or equal to 166 for
1760               window to be visible.
1761 
1762               WX is offset from absolute screen coordinates
1763               by 7. Setting the window to WX=7, WY=0 will
1764               put the upper left corner of the window at
1765               absolute screen coordinates 0,0.
1766 
1767 
1768               Lets say WY = 70 and WX = 87.
1769               The window would be positioned as so:
1770 
1771                0                  80               159
1772                ______________________________________
1773             0 |                                      |
1774               |                   |                  |
1775               |                                      |
1776               |         Background Display           |
1777               |               Here                   |
1778               |                                      |
1779               |                                      |
1780            70 |         -         +------------------|
1781               |                   | 80,70            |
1782               |                   |                  |
1783               |                   |  Window Display  |
1784               |                   |       Here       |
1785               |                   |                  |
1786               |                   |                  |
1787           143 |___________________|__________________|
1788 
1789 
1790           OBJ Characters (Sprites) can still enter the
1791           window. None of the window colors are
1792           transparent so any background tiles under the
1793           window are hidden.
1794 
1795 FFFF
1796    Name     - IE
1797    Contents - Interrupt Enable (R/W)
1798 
1799               Bit 4: Transition from High to Low of Pin
1800                      number P10-P13.
1801               Bit 3: Serial I/O transfer complete
1802               Bit 2: Timer Overflow
1803               Bit 1: LCDC (see STAT)
1804               Bit 0: V-Blank
1805 
1806               0: disable
1807               1: enable

Attached Files

To refer to attachments on a page, use attachment:filename, as shown below in the list of files. Do NOT use the URL of the [get] link, since this is subject to change and can break easily.

You are not allowed to attach a file to this page.